1. Field of the Invention
The present invention relates to an apparatus for processing a video signal, and more particularly, to a bitstream decoding apparatus which decodes a video signal compressed according to the Moving Picture Experts Group (MPEG) standard within one clock cycle and converts the compressed video signal into the form of symbols such as video parameters and discrete cosine transform (DCT) coefficients. The present application is based on Korean Patent Application No. 99-10061 which is incorporated herein by reference.
2. Description of the Related Art
Video bitstreams compressed and encoded under the MPEG1 and MPEG2 standards include a fixed length code, a variable length code, and variable length codes of zero run-length and an AC coefficient pair. In a video decoding apparatus, in order to decode the three types of codes mentioned above from a bitstream into processible form, the bitstream undergoes a process of bitstream decoding at an initial step of decoding. The operating speed of the bitstream decoder is mainly determined by how fast it decodes the run-length codes which account for most of the video data. Recently, development of digital television including high-definition television (HDTV) requires transmission of a considerably high-resolution picture, for example, a resolution of 1920.times.1080 pixels per picture.
To speed up the decoding of a video decoding apparatus, it is necessary to increase the speed of the bitstream decoder as well as of the operating clock frequency. However, a conventional bitstream decoder has problems in transmitting a high-resolution picture signal since it takes a long time to decode a fixed length code, a variable length code, and variable length codes of zero run-length and an AC coefficient pair.